Computer system performance may be highly dependent on associated memory system operational efficiency. For example, processing that stalls when data is unavailable can render results at an unacceptably slow rate. Some microprocessors provide aggressive support for Instruction level Parallelism (ILP) and have deep pipelines to keep cycle times low. However, the actual level of ILP and pipelining performance delivered may depend on the accuracy of branch prediction; mispredictions can stall/squash the pipeline.
Many applications include a significant Operating Sytem (OS) component, which can also affect control flow transfer (i.e., branching) in the execution environment. For example, exception-driven, intermittent invocation of OS code may significantly increase branch misprediction in both user and OS (e.g., kernel) code operating contexts. Thus, there is a need to improve the accuracy of program branch prediction mechanisms, especially for systems having a significant OS system component, and/or systems using pipelined processors.